Voltage Controlled Oscillators (VCO) are often used in Phase Lock Loop (PLL) circuits to generate clock signals. A Voltage controlled oscillator (VCO) is typically built by serially connecting a plurality of delay circuits in a loop and connecting to an intermediate node of the delay cell loop to generate a clock signal. This standard design is quite effective for integrated circuit systems with high supply potentials. The differential delay cell and the current starved inverter are examples of implementations used in present integrated circuits to generate clock signals because their inherent design limitation are not exposed in systems with high supply potential. As the speed and power consumption of integrated circuits is improved in next generation designs, present VCOs and their delay cells have great difficulty operating within the high clock speed and low supply potential specifications of the next generation designs.
FIG. 1 shows a delay cell according to the prior art. Differential Delay Cell 100 comprises two common source NMOS transistors 1 and 2 coupled between pull-down transistor 5 and pull-up transistors 3 and 4. Inputs Vp and Vn are used by the PLL to control the transition time of signals through the delay cell, while the Vin and Vout nodes are connected to subsequent delay cells to form the VCO loop. Differential Delay Cell 100 is often preferred for use in VCOs because the delay cell has a superior supply noise rejection and the cell can easily detect input/output voltage swings of subsequent cells. However, detection of input/output voltage swings is difficult to achieve at a low supply potential for Differential Delay Cell 100, thus making use of Differential Delay Cell 100 impractical for PLLs that support integrated circuits with low supply potentials.
Another prior art implementation of a delay cell is shown in FIG. 2. Current Starved Inverter 200 comprises a stacked gate design. PMOS transistor 200 has its source coupled to NMOS transistor 300, this coupled node is the output of the delay cell, while the gates of transistors 200 and 300 are coupled to the input of the delay cell, Vin. To control the pull-up and pull-down currents of Current Starved Inverter 200, PMOS transistor 100 is coupled between supply potential VDD and the drain of PMOS transistor 200 and NMOS transistor 400 is coupled between supply potential GND and the source of NMOS transistor 300. Similar to the design of Differential Delay Cell 100, the PLL can control the delay of signal propagation through Current Starved Inverter 200 by varying the input voltages Vp and Vn coupled to the gates of transistors 100 and 400. By varying the voltages Vp and Vn, the PLL can control the speed in which Current Starved Inverter 200 charges/discharges parasitic capacitance Cout. The CMOS design of the Current Starved Inverter 200 requires that PMOS transistor 100 and NMOS transistor 400 switch between the saturation and the linear region of operation during a transition of input Vin. During VCO operation Vin transitions continuously causing PMOS transistor 100 and NMOS transistor 400 to vary their current demand on the power supplies VDD and GND of Current Starved Inverter 200. The variations in current supply creates noise along the supply potential of the delay cell leading to signal degradation of the Vout node, especially at high frequencies.
The degradation of the Vout node results in phase jitter as the noisy Vout signal is propagated through subsequent delay cells in the VCO, leading to a noisy PLL clock signal which is unusable in integrated circuit design. Because the Current Starved Inverter delay cell designs lead to a noisy Vout signal in a low supply voltage system, it would be desirable to have an improved delay cell with good noise rejection that can operate at a low supply potential and reduce phase jitter.